Method for manufacturing thin film transistor array panel for display device

ABSTRACT

A gate wire including gate lines, gate electrodes, and gate pads and extending in a transverse direction is formed on a substrate. A gate insulating layer is formed thereafter, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. A conductive material is deposited and patterned to form a data wire inducing data lines intersecting the gate lines, source electrodes, drain electrodes, and data pads. A protective layer made of silicon nitride is deposited on the substrate, and an organic insulating layer made of a photosensitive organic insulating material is coated on the protective layer. The organic insulating layer is patterned to form an unevenness pattern on its surface and first contact holes exposing the protective layer opposite the drain electrodes. Subsequently, the surface of the organic insulating layer is treated using inactive gas such as Ar, and then the protective layer is patterned together with the gate insulating layer by photo etch using a photoresist pattern to form contact holes respectively exposing the drain electrodes, the gate pads, and the data pads. Next, indium-tin-oxide or indium-zinc-oxide is deposited and patterned to form transparent electrodes, subsidiary gate pads, and subsidiary data pads respectively connected to the drain electrodes, the gate pads and the data pads. Finally, a reflective conductive material is deposited and patterned to form reflecting films having respective apertures in the pixel area on the transparent electrodes.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a manufacturing method of a thin filmtransistor array panel for a display device.

(b) Description of the Related Art

At present, a liquid crystal display (“LCD”) is one of the most widelyused flat panel displays. An LCD, which includes two panels havingelectrodes and a liquid crystal layer interposed therebetween, controlsthe transmittance of light passing through the liquid crystal layer byrealigning liquid crystal molecules in the liquid crystal layer withvoltages applied to the electrodes. Among these LCDs, the most commonlyused one provides at least one electrode on each panel and includes thinfilm transistors (“TFTs”) switching the voltages applied to theelectrodes.

Generally, a panel with TFTs (“TFT array panel”) includes, in additionto the TFTs, signal wires including gate lines transmitting scanningsignals, data lines transmitting image signals, gate pads transmittingthe scanning signals from external devices to the gate lines, and datapads transmitting the image signals from external devices to the datalines. The TFT array panel further includes pixel electrodeselectrically connected to the TFTs and located in respective pixel areasdefined by the intersections of the gate lines and the data lines.

In a reflective LCD or a transflective LCD, the pixel electrodes aremade of a transparent conductive material such as indium tin oxide(“ITO”) and overlap signal wires to ensure aperture ratio of pixels.Also, an insulating layer made of organic insulating material with lowdielectric constant is formed between the signal wires and the pixelelectrodes to minimize the interference of the signals transferredthrough them.

Moreover, the pixel electrodes of the transflective LCD are made ofusing a reflective conductive material such as Al or Ag as well as ITO,and formed to have embossment for increasing the reflecting ratio of thepixel electrodes. The embossment of the reflecting film is formed byproviding an organic insulating layer with unevenness under the pixelelectrode.

However, adhesiveness between the organic insulating layer and the ITOfilm is deteriorated when forming the ITO film on the insulating layermade of the organic insulating material. To solve the problem theroughness of the surface of the organic insulating layer is increased byperforming a plasma process before depositing the ITO film.

However, contact resistance of a contact exposing the wire to beconnected to the pixel electrode is increased since the organic materialis re-deposited on the wire in the contact during the plasma process.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a TFT array paneland a manufacturing method thereof having good adhesiveness between anITO film and an organic insulating film and minimizing contactresistance of a contact through which ITO is electrically connected to awire.

In order to solve the problems, the present invention forms a protectivelayer under an organic insulating layer and performing surface-treatmentof the organic insulating layer by a plasma process before deposition ofan ITO film under the condition that the protective layer is remained ona wire.

In detail, in a method of manufacturing a thin film transistor arraypanel according to the present invention a gate wire including a gateline and a gate electrode connected to the gate line is formed, a gateinsulating layer is deposited, a semiconductor layer is formed, and adata wire including a data line intersecting the gate lines to define apixel area, a source electrode connected to the data line and placeddose to the gate electrode, and a drain electrode placed opposite thesource electrode with respect to the gate electrodes is formed.Subsequently, a protective layer is deposited, then an organicinsulating layer is formed by spin-coating an organic insulatingmaterial on the protective layer, the organic insulating layer ispatterned to form a first contact hole exposing the protective layeropposite the drain electrode, and a surface of the organic insulatinglayer is treated by plasma process using inactive gas. Also, theprotective layer is patterned to form a second contact hole exposing thedrain electrode and located inside the first contact hole and a pixelelectrode electrically connected to the drain electrode through thefirst and the second contact holes is formed.

The pixel electrode may include a transparent conductive electrode or areflective conductive film. The surface of the organic insulating layerpreferably has an unevenness pattern when the pixel electrode has thereflective film. The reflective film has an aperture in the pixel area.

The semiconductor layer may include amorphous silicon or poly silicon.The protective layer may include SiNx or SiOx. Preferably, the secondcontact hole may be formed by a photo etch using a photoresist patternafter forming the first contact hole.

It is preferable that the gate wire further includes a gate padconnected to one end of the gate line, the data wire further includes adata pad connected to one end of the data line, and the protective layeror the gate insulating layer has a third contact hole exposing the gatepad or the data pad. The thin film transistor array panel preferablyfurther includes a subsidiary pad electrically connected to the gate pador the data pad through the third contact hole and includingsubstantially the same layer as the pixel electrode.

Both the data wire and the semiconductor layer may be formed by a photoetch step using a photoresist pattern with position-dependent thickness.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout view of a TFT array panel for a transflective typeLCD according to a first embodiment of the present invention;

FIG. 2 is a sectional view of FIG. 2 taken along the line II–II′;

FIGS. 3A, 4A, 5A, 6A, 8A and 9A are layout views of a TFT array panelfor a transflective type LCD in the intermediate steps of amanufacturing method thereof according to an embodiment of the presentinvention;

FIG. 3B is a sectional view of the TFT array panel shown in FIG. 3Ataken along the line IIIB–IIIB′;

FIG. 4B is a sectional view of the TFT array panel shown in FIG. 4Ataken along the line IV–IV′ and illustrates the step following the stepshown in FIG. 3B;

FIG. 5B is a sectional view of the TFT array panel shown in FIG. 5Ataken along the line VB–VB′ and illustrates the step following the stepshown in FIG. 4B;

FIG. 6B is a sectional view of the TFT array panel shown in FIG. 6Ataken along the line VIB–VIB′ and illustrates the step following thestep shown in FIG. 5B;

FIG. 7 is a sectional view of the TFT array panel shown in FIG. 6A takenalong the line VIB–VIB′ and illustrates the step following the stepshown in FIG. 6B;

FIG. 8B is a sectional view of the TFT array panel shown in FIG. 8Ataken along the line VIIIB–VIIIB′ and illustrates the step following thestep shown in FIG. 7;

FIG. 9B is a sectional view of the TFT array panel shown in FIG. 9Ataken along the line IXB–IXB′ and illustrates the step following thestep shown in FIG. 8B;

FIG. 10 is a layout view of a TFT array panel for a reflective type LCDaccording to a second embodiment of the present invention;

FIG. 11 is a sectional view of the TFT array panel shown in FIG. 10taken along the line XI–XI′;

FIG. 12 is a layout view of a TFT array panel for an LCD according to athird embodiment of the present invention;

FIGS. 13 and 14 are sectional views of the TFT array panel shown in FIG.12 taken along the line XIII–XIII′ and the line XIV–XIV′, respectively;

FIG. 15A is a layout view of a TFT array panel in the first step of amanufacturing method thereof according to the third embodiment of thepresent invention;

FIGS. 15B and 15C are sectional views of the TFT array panel shown inFIG. 15A taken along the lines XVB–XVB′ and XVC–XVC′, respectively;

FIGS. 16A and 16B are sectional views of the TFT array panel shown inFIG. 15A taken along the lines XVB–XVB′ and XVC–XVC′, respectively, andillustrate the step following the step shown in FIGS. 15B and 15C;

FIG. 17A is a layout view of the TFT array panel in the step followingthe step shown in FIGS. 16A and 16B;

FIGS. 17B and 17C are sectional views of the TFT array panel shown inFIG. 17A taken along the lines XVIIB–XVIIB′ and XVIIC–XVIIC′,respectively;

FIGS. 18A, 19A and 20A and FIGS. 18B, 19B and 20B are respectivesectional views of the TFT array panel shown in FIG. 17A taken along thelines XVIIB–XVIIB′ and XVIIC–XVIIC′, respectively, and illustrate thesteps following the step shown in FIGS. 17B and 17C;

FIG. 21A is a layout view of the TFT array panel in the step followingthe step shown in FIGS. 20A and 20B;

FIGS. 21B and 21C are sectional views of the TFT array panel shown inFIG. 21A taken along the lines XXIB–XXIB′ and XXIC–XXIC′, respectively;

FIG. 22A is a layout view of the TFT array panel in the step followingthe step shown in FIGS. 21B and 21C; and

FIGS. 22B and 22C are sectional views of the TFT array panel shown inFIG. 22A taken along the lines XXIIB–XXIIB′ and XXIIC–XXIIC′ andillustrate the sequence of the step following the step shown in FIGS.21B and 21C, respectively.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Now, TFT array panels and manufacturing methods thereof according toembodiments of the present invention will be described with reference tothe accompanying drawings, which makes those skilled in the art toeasily carry out the present invention.

First, a transflective type LCD according to a first embodiment of thepresent invention will be described in detail with reference to FIGS. 1and 2.

FIG. 1 is a layout view of a TFT array panel for a transflective typeLCD according to a first embodiment of the present invention, and FIG. 2is a sectional view of the TFT array panel shown in FIG. 1 taken alongthe line II–II′.

A gate wire is formed on an insulating substrate 10. The gate wireincludes either a single layer preferably made of Ag, Ag alloy, Al andAl alloy having low resistivity, or multiple layers including the singlelayer. The gate wire includes a plurality of gate lines 22 extendingsubstantially in a transverse direction, a plurality of gate pads 24connected to one ends of the gate lines 22 for receiving gate signalsfrom external devices and transmitting the gate signals to the gatelines 22, and a plurality of gate electrodes 26 of TFTs connected to thegate lines 22. The gate wire may overlap pixel electrodes 82 and 86,which will be formed later, to form storage capacitors, or may include aplurality of storage electrodes applied with a predetermined voltagesuch as a common electrode voltage (which is applied to a commonelectrode of an upper panel and referred to as “a common voltage”hereinafter) from an external source such that the storage electrodesoverlap the pixel electrodes 82 and 86, which will be described later,to form storage capacitors for improving the charge storing capacity ofpixels.

The gate wire 22, 24 and 26 is covered by a gate insulating layer 30preferably made of SiNx formed on the substrate 10.

A semiconductor pattern 40 preferably made of amorphous silicon isformed on the gate insulating layer 30 opposite the gate electrodes 24,and an ohmic contact layer pattern 55 and 56 preferably made of silicideor n+ hydrogenated amorphous silicon heavily doped with n type impurityis formed on the semiconductor pattern 40.

A data wire is formed on the ohmic contact layer pattern 55 and 56 andthe gate insulating layer 30. The data wire includes a conductive layerpreferably made of conductive material with low resistivity such as Aland Ag. The data wire includes a plurality of data lines 62 extendingsubstantially in a longitudinal direction and intersecting the gatelines 22 to define pixel areas, a plurality of source electrodes 65connected to the data lines 62 and extending to one portions 55 of theohmic contact layer pattern, a plurality of data pads 68 connected toone ends of the data lines 62 for receiving image signals from externaldevices, and a plurality of drain electrodes 66 separated from thesource electrodes 65 and located on the other portions 56 of the ohmiccontact layer pattern opposite the source electrodes 65 with respect tothe gate electrodes 26.

A protective layer 70 preferably made of SiNx is formed on the data wire62, 65, 66 and 68 and portions of the semiconductor pattern 40, whichare not covered by the data wire 62, 65, 66 and 68, and an organicinsulating layer 90 is formed on the protective layer 70. The organicinsulating layer 90 is preferably made of photosensitive organicmaterial having a good flatness characteristic. The top surface of theorganic layer 90 has an evenness pattern to maximize the reflectingefficiency of a reflecting film 86, which will be described later. Atpad areas with the gate pads 24 and the data pads 68, the organicinsulating layer 90 is removed out, while the protective layer 70 isstill remained. This structure removes organic insulating material onthe pad areas and thus is advantageously applicable to a chip on glass(“COG”) type LCD, where a plurality of gate driving integrated circuits(“ICs”) and a plurality of data driving ICs for respectivelytransmitting the scanning signals and the image signals to the gate pads24 and the data pads 68 are directly mounted on the TFT array panel.

A plurality of contact holes 76 and 78 respectively exposing the drainelectrodes 66 and the data pads 68 are provided at the protective layer70, and a plurality of contact holes 74 exposing the gate pads 24 areprovided at the gate insulating layer 30 and the organic insulatinglayers 90. The organic insulating layer 90 has a plurality of contactholes 96 exposing the drain electrodes 66, the boundaries of the contactholes 76 of the protective layer 70 exposing the drain electrodes 66,and the flat surface of the protective layer 70.

A plurality of transparent electrodes 82 are formed on the organicinsulating layer 90. The transparent electrodes 82 are locatedsubstantially in a pixel area, and electrically connected to the drainelectrodes 66 through the contact holes 76 and 96. A reflecting film 86having an aperture 85 is formed on each transparent electrode 82. Amongthe pixel area P, an area T defined by the aperture 85 is referred to asa transmitting area, while the remaining area R is referred to as areflecting area. The transparent electrodes 82 are preferably made oftransparent conductive material such as indium zinc oxide (“IZO”) andindium tin oxide (“ITO”), while the reflecting films 86 are preferablymade of Al, Al alloy, Ag and Ag alloy having reflectance. Eachreflecting film 86 preferably includes a contact assistant layerprovided on a contact surface with the transparent electrode 82 toensure good contact characteristics between the reflecting film 86 andthe transparent electrode 82, and the contact assistant layer ispreferably made of Mo, Mo alloy, Cr, Ti or Ta.

Furthermore, a plurality of subsidiary gate pads 84 and a plurality ofsubsidiary data pads 88 are formed on the protective layer 70. Thesubsidiary gate pads 84 and the subsidiary data pads 88 are connected tothe gate and the data pads 24 and 68 through the contact holes 74 and78, respectively. Although the subsidiary gate and data pads 84 and 88are not requisites but preferred to protect the gate and the data pads24 and 68. The subsidiary gate and data pads 84 and 88 are preferablymade of the same layer either as the transparent electrodes 82 or as thereflecting film 86.

A method of manufacturing a TFT array panel for a transflective type LCDaccording to the first embodiment of the present invention will be nowdescribed with reference to FIGS. 3A to 8B as well as FIGS. 1 and 2.

As shown in FIGS. 3A and 3B, a conductive material with low resistivityis deposited on a glass substrate 10, and patterned by photo etch usinga mask to form a gate wire extending substantially in the transversedirection including a plurality of gate lines 22, a plurality of gateelectrodes 26, and a plurality of gate pads 24.

Next, as shown in FIGS. 4A and 4B, after sequentially depositing threelayers including a gate insulating layer 30 made of SiNx, asemiconductor layer 40 made of amorphous silicon, and a doped amorphoussilicon layer 50, the doped amorphous silicon layer 50 and thesemiconductor layer 40 are patterned by photo etch using a mask to forma semiconductor pattern 40 and a doped amorphous silicon layer pattern50 on the gate insulating layer 30 opposite the gate electrodes 24. Atthat time, the semiconductor pattern 40 may be formed along the datalines 62 which are described later.

Subsequently, as shown in FIGS. 5A and 5B, a conductive layer for a datawire is deposited and patterned by photolithography using a mask to forma data wire including a plurality of data lines 65 intersecting the gatelines 22, a plurality of source electrodes 65 connected to the datalines 65 and extending onto the gate electrodes 26, a plurality of datapads 68 connected to one ends of the data lines 62, and a plurality ofdrain electrodes 66 separated from the source electrodes 65 and oppositethe source electrodes 65 with respect to the gate electrodes 26.

Thereafter, portions of the doped amorphous silicon pattern 50, whichare not covered by the data wire 62, 65, 66 and 68, are etched such thatthe doped amorphous silicon layer pattern 50 is separated into twoportions 55 and 56 opposite each other with respect to the gateelectrodes 26 to expose portions of the semiconductor pattern 40 betweenthe two portions of the doped amorphous silicon layer pattern 55 and 56.Oxygen plasma treatment is preferably performed in order to stabilizethe exposed surfaces of the semiconductor pattern 40.

As shown in FIGS. 6A and 6B, SiNx is deposited by CVD to form aprotective layer 70, and a photosensitive organic material having a goodflatness characteristic is coated on the protective layer 70 to form anorganic insulating layer 90 before patterning the protective layer 70.Thus, the spin-coating of the organic insulating layer 90 beforepatterning the protective layer 70 prevents the localized distributionof organic material onto a specific area since there is no heightdifference due to the protective layer 70 during the spin coating.Thereafter, the organic insulating layer 90 is patterned byphotolithography using a mask to form a plurality of contact holes 96exposing portions of the protective layer 70 opposite the drainelectrodes 66 and simultaneously to form an unevenness pattern on thesurface of the organic insulating layer 90. Furthermore, portions of theorganic insulating layer 90 at the pad areas provided with the gate pads24 and the data pads 68 are removed to expose the protective layer 70.

Subsequently, as shown in FIG. 7, a plasma process using Ar gas isexecuted to enhance surface roughness of the organic insulating layer 90before patterning the protective layer 70. Here, Ar gas may be replacedwith inactive gas such as N2, He, Ne, Kr and Xe. The surface roughnessof the organic insulating layer 90 is enhanced by the plasma process toimprove the adhesiveness of an ITO film 82 which will be describedlater. According to an embodiment of the present invention, since theplasma process is executed before patterning the protective layer 70,the gate lines or the data lines which may be exposed later on a contactare not injured.

Subsequently, as shown in FIGS. 8A and 8B, the protective layer 70 andthe gate insulating layer 30 are patterned by photo etch using aphotoresist pattern 1000 to form a plurality of contact holes 74, 76 and78 exposing the gate pads 24, the drain electrodes 66, and the data pads68, respectively. The contact holes 76 of the protective layer 70exposing the drain electrodes 66 are placed inside the contact holes 96of the organic insulating layer 90 such that the boundaries and the flatsurfaces of the protective layer 70 are exposed, and therefore thecontact structures have stepwise shapes without undercut It ispreferable that the width of the exposed surface of the protective layer70 at the contact structure is 0.1 microns or more.

When the data wire 62, 65, 66 and 68 or the gate wire 22, 24 and 26 havemultiple layers and the top layer of the data wire 62, 65, 66 and 68 orthe gate wire 22, 24 and 26 is formed of Al or Al alloy, the top layeris removed to prevent the top layer of Al or Al alloy from contacting anITO film, which will be formed later, at a contact.

Next, as shown in FIGS. 9A and 9B, ITO is deposited and patterned usinga mask to form a plurality of transparent electrodes 82 connected to thedrain electrodes 66 through the contact holes 76 and 96, a plurality ofsubsidiary gate pads 84 connected to the gate pads 24 through thecontact holes 74, and a plurality of subsidiary data pads 88 connectedto the data pads 68 through the contact holes 78.

A manufacturing method of a TFT array panel according to the firstembodiment of the present invention prevents the wires from beingdamaged at a contact by performing plasma process before the protectivelayer 70 is removed at the contact, as described above. In addition,organic insulating material remaining inside the contact holes 76, 96,74 and 78 is completely removed by performing plasma process forsurface-treating the organic insulating layer 90 before patterning theprotective layer 70 by photo etch for forming the contact holes 74, 76and 78 at the protective layer 70. Therefore, contact resistance at acontact is minimized and inactive gas which may be remained during theplasma process is completely removed.

Finally, as shown in FIGS. 1 and 2, a reflective conductive materialincluding Ag or Al with reflectance is deposited and patterned by photoetch using a mask to form a plurality of reflecting films 86 on therespective transparent electrodes 82. At this time, each reflecting film86 preferably includes a contact assistant layer made of material havinga good contact characteristic with other materials to improve thecontact characteristic with the transparent electrode 82.

According to the first embodiment of the present invention, thespin-coating of the organic insulating layer 90 before patterning theprotective layer 70 prevents the localized distribution of organicmaterial onto a specific area since there is no height difference due tothe protective layer 70 during the spin coating, thereby obtaining auniform unevenness pattern on the organic insulating layer 90. As aresult, the embossment of the reflecting film 86 following theunevenness pattern of the organic insulating layer 90 is established tobe uniform, and this prevents stains on a screen displaying images.

The method of manufacturing a TFT array panel according to thisembodiment of the present invention completely prevents organicinsulating material from remaining on the pad areas because theprotective layer 70 is patterned after removing the organic insulatingmaterial from the pad areas in the formation of the organic insulatinglayer 90. Therefore, the TFT array panel manufactured by this method isadvantageously applicable particularly to a COG type LCD, where aplurality of gate driving ICs and a plurality of data driving ICs forrespectively transmitting the scanning signals and the image signals tothe gate pads 24 and the data pads 68 are directly mounted on the TFTarray panel.

In the meantime, the manufacturing method according to the firstembodiment of the present invention can be adapted to a method formanufacturing a TFT array panel for a reflective type LCD.

A TFT array panel for a reflective type LCD according to a secondembodiment of the present invention will be described in detail withreference to FIGS. 10 and 11.

As shown in FIGS. 10 and 11, the structure is almost the same as thestructure according to the first embodiment.

However, different from the first embodiment, a plurality of reflectingfilms 86 are located directly on an organic insulating layer 90 and indirect electrical connection with a plurality of drain electrodes 66through a plurality of contact holes 76 and 96. In addition, thereflecting film 86 occupies the entire pixel area.

Moreover, a plurality of gate wire 22, 24 and 26 and a plurality of datawire 62, 65 and 66 overlap relevant pixel electrodes 82 via the organicinsulating layer 90 with low dielectric constant to give maximumaperture ratio.

Furthermore, a data wire 62, 65, 66 and 68 includes a conductor pattern64 for storage capacitors overlapping the gate lines 22, and the pixelelectrodes 82 made of a transparent conductive material are placeddirectly on an organic insulating layer 90. The pixel electrodes arelocated substantially in pixel areas and electrically connected to aplurality of drain electrode 66 through contact holes 76 and 96. Thepixel electrodes 82 are electrically connected to the conductor pattern64 through contact holes 72 and 92 provided at the protective layer 70and the organic insulating layer 90, and contact holes 74 provided atthe protective layer 70 and a gate insulating layer 30 exposing gatepads 24 are wider than the gate pads 24.

A method of manufacturing a TFT array panel for a transmissive type LCDaccording to the second embodiment of the present invention is almostthe same as the method according to the first embodiment, until the stepof forming contact holes 72, 74, 76 and 78 at a protective layer 70.

The method of manufacturing the TFT array panel according to the secondembodiment of the present invention provides a semiconductor layer 40extending in the longitudinal direction along the data wire 62, 65, 66and 68, and does not form an unevenness pattern on the surface of anorganic insulating layer 90.

The above-described manufacturing method according to the embodiments ofthe present invention can be applied to a method of manufacturing a TFTarray panel for a transmissive type LCD forming both a semiconductorlayer and a data wire by photo etch using one photoresist pattern,thereby simplifying the manufacturing process. This method will bedescribed in detail with reference to accompanying drawings.

First, a structure of a unit pixel of a TFT array panel for an LCDmanufactured using four masks according to an embodiment of the presentinvention will be described with reference to FIGS. 12 to 14.

FIG. 12 is a layout view of a TFT array panel for an LCD according to afourth embodiment of the present invention, and FIGS. 13 and 14 aresectional views of the TFT array panel shown in FIG. 12 taken along theline XIII–XIII′ and the line XIV–XIV′ of FIG. 12, respectively.

As in the second embodiment, a gate wire is formed on an insulatingsubstrate 10. The gate wire is preferably made of a material with lowresistivity such as Ag, Ag alloy, Al and Al alloy. The gate wireincludes a plurality of gate lines 22, a plurality of gate pads 24, anda plurality of gate electrodes 26. The gate wire further includes aplurality of storage electrodes 28 formed on the substrate, which aresubstantially parallel to the gate lines 22 and applied with apredetermined voltage such as a common voltage from an external source,which is also applied to a common electrode of an upper panel. Thestorage electrodes 28 overlap a storage capacitor conductor patternconnected to pixel electrodes 82, which will be described later, to formstorage capacitors for improving the charge storing capacity of pixels.The storage electrodes 28 may be omitted if the storage capacitance dueto the overlapping of the gate lines 22 and the pixel electrodes 82 tobe described later are sufficient.

A gate insulating layer 30 preferably made of silicon nitride is formedon the gate wire 22, 24, 26 and 28, while covering the gate wire 22, 24,26 and 28.

A semiconductor pattern 42 and 48 preferably made of hydrogenatedamorphous silicon is formed on the gate insulating layer 30, and anohmic contact layer pattern or an intermediate layer pattern 55, 56 and58 preferably made of amorphous silicon heavily doped with n typeimpurity such as phosphorous is formed on the semiconductor layer 42 and48.

A data wire made of an aluminum-based conductive material with lowresistivity is formed on the ohmic contact layer pattern 55, 56 and 58.The data wire includes a plurality of data portions 62, 65 and 68, aplurality of drain electrodes 66 of TFTs, and a storage capacitorconductor pattern 64. Each data portion includes a data line 62extending substantially in the longitudinal direction, a data pad 68connected to one end of the data line 62 for receiving image signalsfrom an external device, and a plurality of source electrodes 65branched from the data line 62. Each drain electrode 66 is separatedfrom the data portion 62, 65 and 68, and placed opposite thecorresponding source electrode 53 with respect to the corresponding gateelectrode 26 or a channel portion of the associated TFT. The storagecapacitor conductor pattern 64 is placed on the storage electrodes 28.In absence of the storage electrodes 28, the storage capacitor conductorpattern 64 is not provided.

The ohmic contact layer pattern 55, 56 and 58 plays a role of reducingthe contact resistance between the semiconductor pattern 42 and 48thereunder and the data wire 62, 64, 65, 66 and 68 thereover. The ohmiccontact layer pattern 55, 56 and 58 has substantially the same shape asthe data wire 62, 64, 65, 66 and 68. In detail, a data intermediatelayer pattern 55 of the have substantially the same shapes as the dataportions 62, 65 and 68, a drain intermediate layer pattern 56 as thedrain electrodes 66, and a storage capacitor intermediate layer pattern58 as the storage capacitor conductor pattern 68.

The semiconductor pattern 42 and 48 has the same shape as the data wire62, 64, 65, 66 and 68 and the ohmic contact layer pattern 55, 56 and 58except for the channel areas C of the TFTs. Specifically, a storagecapacitor semiconductor pattern 48 has substantially the same shape asthe storage capacitor conductor pattern 64 and the storage capacitorohmic contact layer pattern 58, while a TFT semiconductor pattern 42layer is a little different from the data wire and the rest of the ohmiccontact layer pattern. On the channel areas C of each TFT, although thedata portions 62, 65 and 68, especially the source electrodes 65 areseparated from the drain electrodes 66, and the data intermediate layerpattern 55 is also separated from the drain ohmic contact layer pattern56, the TFT semiconductor pattern 42 is not disconnected to formchannels of the TFTs.

An interlayer insulator including a protective layer 70 preferably madeof silicon nitride and an organic insulating layer 90 preferably made oforganic insulating material with low permittivity is provided on thedata wire 62, 65, 66 and 68 as in the first embodiment. The protectivelayer 70 has a plurality of contact holes 76, 78 and 72 exposing thedrain electrodes 66, the data pads 68, and the storage capacitorconductor pattern 64, respectively, and a plurality of contact holes 74exposing the gate pads 24 together with the gate insulating layer 30.Like the first embodiment, the organic insulating layer 90 is removedout from the pad areas to expose the protective layer 70, and thecontact holes 92 and 96 expose the boundaries of the protective layer70, which is a lower insulating layer, such that the sidewalls of thecontact holes 72, 92; and 76, 96 have stepwise shapes.

A plurality of pixel electrodes 82 receiving image signals from the TFTsand generating electric fields in cooperation with an electrode on anupper panel are formed on the organic insulating layer 90. The pixelelectrodes 82 are made of transparent conductive material such as IZO orITO, and electrically connected to the drain electrodes 66 through thecontact holes 76 and 96 to receive image signals. Furthermore, the pixelelectrodes 82 overlap the adjacent gate lines 22 and the adjacent datalines 62 to increase the aperture ratio. However, the overlaps may beomitted. The pixel electrodes 82 are connected to the storage capacitorconductor pattern 64 through the contact holes 72 and 92 to transmit theimage signals.

A plurality of subsidiary gate pads 84 and a plurality of subsidiarydata pads 88 are formed on the protective layer 70. The subsidiary gatepads 84 and the subsidiary data pads 88 are located on the gate pads 24and the data pads 24 and 68, respectively, and thus connected theretothrough the contact holes 74 and 78, respectively. Although thesubsidiary gate pads 84 and the subsidiary data pads 88 are notrequisites but preferred to protect the pads 24 and 68 and to complementthe adhesiveness between the pads 24 and 68 and external circuitdevices. The contact structure has no undercut and thus prevents thedisconnections of the pixel electrodes 82, the subsidiary gate pads 84,and the subsidiary data pads 88. The subsidiary gate pads 84 and thesubsidiary data pads 88 are located on the protective layer 70 at leastin part.

Now, a method of manufacturing a TFT array panel for an LCD having thestructure shown in FIGS. 12–14 using four masks will be described indetail with reference to FIGS. 12–14 and FIGS. 15A–22C.

First, as shown in FIGS. 15A–15C, a gate wire including a plurality ofgate lines 22, a plurality of gate pads 24, a plurality of gateelectrodes 26, and a plurality of storage electrodes 28 is formed on asubstrate 10 by depositing a conductive material or materials for thegate wire and patterning by photo etch using a first mask. The gate wirehas a single-layered structure including a single layer made of materialwith low resistivity such as Al, Al alloy, Ag or Ag alloy.Alternatively, the conductive layer has a multiple-layered structureincluding the single layer and a layer made of conductive material withgood contact characteristics with other materials, such as Cr, Ti, andTa.

Next, as shown in FIGS. 16A and 16B, a gate insulating layer 30, asemiconductor layer 40, and an intermediate layer 50 are sequentiallydeposited by CVD such that the layers 30, 40 and 50 bear thickness of1,500–5,000 Å, 500–2,000 Å and 300–600 Å, respectively. A conductivelayer 60 for a data wire with low resistivity is deposited by sputteringsuch that the layer 60 bears the thickness of 1,500–3,000 Å, andsubsequently a photoresist film 110 with the thickness of 1–2 microns iscoated on the conductive layer 60.

Subsequently, the photoresist film 110 is exposed to light through asecond mask, and developed to form a photoresist pattern 114 and 112 asshown in FIGS. 17A–17C. First portions 114 of the photoresist pattern114 and 112, which are located on channel areas C of TFTs between sourceand drain electrodes 65 and 66, are established to bear thicknesssmaller than that of the second portions 112 on data areas A where thedata wire 62, 64, 65, 66 and 68 is formed. The portions of thephotoresist film on the remaining area B are removed. The thicknessratio of the first portions 114 on the channel areas C to the secondportions 112 on the data areas A is adjusted depending upon the etchingconditions in the etching steps to be described later. It is preferablethat the thickness of the first portions 114 is equal to or less thanhalf of the thickness of the second portions 112, in particular, equalto or less than 4,000 Å.

The position-dependent thickness of the photoresist film is obtained byseveral techniques. In order to adjust the amount of light exposure inthe areas C, semi-transparent areas having a slit pattern, a latticepattern or semi-transparent films are provided on a mask.

When using a slit pattern, it is preferable that the width of theportions between the slits or the distance between the portions, i.e.,the width of the slits is smaller than the resolution of an exposer usedfor the photolithography. In case of using semi-transparent films, thinfilms with different transmittances or with different thicknesses may beused to adjust the transmittance of the mask.

When the photoresistive film is irradiated with light through such amask, polymers of the portions directly exposed to the light are almostcompletely decomposed, and those of the portions facing the slit patternor the semi-transparent films are not completely decomposed due to thesmall amount of light exposure. The polymers of the portions blocked bylight-blocking films are hardly decomposed. Development of thephotoresistive film makes the portions having the polymers, which arenot decomposed, to be left, and makes the portions exposed to thesmaller light irradiation to be thinner than the portions which do notexperience the light exposure. Here, it is required not to make theexposure time long enough to decompose all the molecules.

The thin portions 114 of the photoresist pattern may be obtained byperforming a reflow process to flow a reflowable photoresist film intothe areas without the photoresist film after exposing to light anddeveloping the photoresist film, using a usual mask with transmissiveareas completely transmitting the light and blocking areas completelyblocking the light.

Thereafter, the photoresist pattern 114 and the underlying layers, i.e.,the conductive layer 60, the intermediate layer 50 and the semiconductorlayer 40 are etched such that a data wire and the underlying layers areleft over on the data areas A, only the semiconductor layer is left overon the channel areas C, and all of the three layers 60, 50 and 40 areremoved from the remaining areas B to expose the gate insulating layer30.

As shown in FIGS. 18A and 18B, the exposed portions of the conductivelayer 60 on the areas B are removed to expose the underlying portions ofthe intermediate layer 50. In this step, both dry etching and wetetching is selectively used and preferably performed under the conditionthat the conductive layer 60 is selectively etched while the photoresistpattern 112 and 114 is hardly etched. However, an etching conditioncapable of etching the photoresist pattern 112 and 114 as well as theconductive layer 60 would be suitable for dry etching since it isdifficult to find a condition for selectively etching only theconductive layer 60 while not etching the photoresist pattern 112 and114. In this case, the first portion 114 should have relatively thickcompared with that for wet etching in order to prevent the exposure ofthe underlying conductive layer 60 through the etching.

Both dry etching and wet etching are applicable to the conductivematerial for a data wire containing Al or Al alloy. Wet etching,preferably with an etchant CeNHO3, is preferred for Cr which is hardlyremoved by dry etching. However, a very thin Cr film of about 500 Å maybe removed by dry etching.

Consequently, as shown in FIGS. 18A and 18B, a source/drain conductorpattern 67, i.e., portions of the conductive layer on the channel areasC and the data areas A, and a storage capacitor conductor pattern 64 areleft over, while portions of the conductive layer 60 on the remainingareas B is removed out to expose the underlying portions of theintermediate layer 50. The remaining conductor patterns 67 and 64 havesubstantially the same shapes as the data wire 62, 64, 65, 66 and 68except that the source and the drain electrodes 65 and 66 are stillconnected without separation. When using the dry etching, thephotoresist pattern 112 and 114 are also etched to a predeterminedthickness.

Next, as shown in FIGS. 19A and 19B, the exposed portions of theintermediate layer 50 on the areas B and the underlying portions of thesemiconductor layer 40 are simultaneously removed by dry etchingtogether with the first portions 114 of the photoresist pattern.Sequential dry etch of the intermediate layer 50 and the semiconductorlayer 40 may follow the dry etch of the conductor patterns 64 and 67 orin-situ etch process may be performed. The etch of the intermediatelayer 50 and the semiconductor layer 40 is preferably made in acondition that the photoresist pattern 112 and 114, the intermediatelayer 50 and the semiconductor layer 40 are simultaneously etched whilethe gate insulating layer 30 is not etched. (It is noted that thesemiconductor layer and the intermediate layer have no etchingselectivity.) Particularly, the etching ratios of the photoresistpattern 112 and 114 and the semiconductor layer 40 are preferably equalto each other. For the equal etching ratios of the photoresist pattern112 and 114 and the semiconductor layer 40, the thickness of the firstportions 114 is preferably equal to or less than the sum of thethicknesses of the semiconductor layer 40 and the intermediate layer 50.

In this way, as shown in FIGS. 19A and 19B, the portions of theconductive layer 60 on the channel areas C and the data areas A, i.e.,the source/drain conductor pattern 67 and the storage capacitorconductor pattern 64 are left over, while the portions of the conductivelayer 60 on the remaining areas B are removed out. Moreover, the firstportions 114 on the channel areas C are removed to expose thesource/drain conductor pattern 67, and the portions of the intermediatelayer 50 and the semiconductor layer 40 on the areas B are removed toexpose the underlying portions of the gate insulating layer 30.Meanwhile, the second portions 112 on the data areas A are also etchedto have reduced thickness. In this step, the formation of asemiconductor pattern 42 and 48 are completed. Reference numerals 57 and58 indicate intermediate layer patterns under the source/drain conductorpattern 67 and under the storage capacitor conductor pattern 64,respectively. The exposure of the portions of the source/drain conductorpattern 67 on the channel areas C is alternatively obtained by aseparate photoresist (“PR”) etch back step, which is not necessary underthe condition that the photoresist film is sufficiently etched.

Residual photoresist remained on the surface of the source/drainconductor pattern 67 on the channel areas C is then removed by ashing.

Subsequently, as shown in FIGS. 20A and 20B, the exposed portions of thesource/drain conductor pattern 67 on the channel areas C and theunderlying portions of the source/drain intermediate layer pattern 57are etched to be removed. Dry etching may be applied to both of thesource/drain conductor pattern 67 and the source/drain intermediatelayer pattern 57. Alternatively, wet etching is applied to thesource/drain conductor pattern 67 while dry etching is applied to thesource/drain intermediate layer pattern 57. At this time, as shown inFIG. 15B, top portions of the semiconductor pattern 42 may be removed tocause thickness reduction, and the second portions 112 of thephotoresist pattern is etched to a predetermined thickness. The etchingis performed under the condition that the gate insulating layer 30 ishardly etched, and it is preferable that the photoresist film is sothick to prevent the second portion 112 from being etched to expose theunderlying data wire 62, 64, 65, 66 and 68.

In this way, the source and the drain electrodes 65 and 66 are separatedfrom each other while completing the formation of the data wire 62, 64,65, 66 and 68 and the underlying ohmic contact layer pattern 55, 56 and58.

Finally, the second portions 112 remained on the data areas A areremoved. However, the removal of the second portions 112 may be madebetween the removal of the portions of the source/drain conductorpattern 67 on the channel areas C and the removal of the underlyingportions of the intermediate layer pattern 57.

After the data wire 62, 64, 65, 66 and 68 is formed as described above,silicon nitride is deposited by CVD to form a protective layer 70 asshown in FIGS. 21A–21C. An organic insulating layer 90 is formed on theprotective layer 70 by spin-coating photosensitive organic materialhaving a good flatness characteristic and low permittivity beforepatterning the protective layer 70. The spin-coating of the organicinsulating layer 90 before patterning the protective layer 70 accordingto this embodiment of the present invention prevents the localizeddistribution of the organic insulating layer 90 onto a specific areabecause there is no height difference due to the protective layer 70during the spin coating. Thereafter, the organic insulating layer 90 ispatterned by photolithography using a mask to form a plurality ofcontact holes 96 and 92 exposing portions of the protective layer 70 onthe drain electrodes 66 and the storage capacitor conductor pattern 64.At this time, the portions the organic insulating layer 90 at the padareas with the gate pads 24 or the data pads 68 are removed to exposethe protective layer 70.

Subsequently, as shown in FIGS. 21B and 21C, the plasma process usinginactive gas such as Ar is performed to enhance the surface roughness ofthe organic insulating layer 90. As a result, a contact area between thepixel electrode 82, which will be formed later, and the organicinsulating layer 90 is increased to ensure the adhesivenesstherebetween. The plasma process performed before patterning theprotective layer 70 may prevent the organic material from remainingdirectly on the signal wires 66, 64, 24 and 68.

Referring to FIGS. 22A to 22C, as in the first embodiment, theprotective layer 70 as well as the gate insulating layer 30 is patternedby photo etch using a photoresist pattern to form a plurality of contactholes 74, 76, 72 and 78 exposing the gate pads 24, the drain electrodes66, the storage capacitor conductor pattern 64 and the data pads 68,respectively. The contact holes 76 and 72 of the protective layer 70exposing the drain electrodes 66 and the storage capacitor conductorpattern 64 are placed inside the contact holes 96 and 92 of the organicinsulating layer 90.

According to manufacturing methods of the embodiments of the presentinvention, although the organic material is re-deposited to remain onthe exposed portions of the protective layer 70 by the previous plasmaprocess, the organic material remnants at contacts including the contactholes 74, 76, 72 and 78 is almost removed in the pattering step of theprotective layer 70 for forming the contact holes 74, 76, 72 and 78.Furthermore, since the protective layer 90 is patterned after performingthe plasma process, remaining gas used in the plasma process is almostremoved.

When the data wire 62, 64, 65, 66 and 68 or the gate wire 22, 24, 26 and28 have multiple layers and the top layer of the data wire 62, 65, 66and 68 or the gate wire 22, 24 and 26 is formed of Al or Al alloy, thetop layer is removed to prevent the top layer of Al or Al alloy fromcontacting an ITO film, which will be formed later, at a contact.

Finally, after removing the photoresist pattern, as shown in FIGS. 12 to14 like the first and the second embodiments of the present invention,ITO or IZO with a thickness of 400–500 Å is deposited and etched using afourth mask to form a plurality of pixel electrodes 82 connected to thedrain electrodes 66 and the storage capacitor conductor pattern 64, aplurality of subsidiary gate pads 84 connected to the gate pads 24, anda plurality of subsidiary data pads 84 and 88 connected to the data pads68.

The third embodiment of the present invention provides not only theadvantages according to the first embodiment ensuring the adhesivenessbetween the organic insulating layer 90 and the pixel electrode 82 andminimizing the contact resistance at a contact but also a simplifiedprocess that the data wire 62, 64, 65, 66 and 68, the ohmic contactlayer pattern 55, 56 and 58 and the semiconductor pattern 42 and 48thereunder are formed using one mask, and simultaneously, the source andthe drain electrodes 65 and 66 are separated from each other in thisstep.

The connection between driving ICs and pads of a TFT array panel for anLCD manufactured by these methods is implemented by using TCPs withdriving ICs mounted on respective films or by means of the COP style.Alternatively, the electrical connection therebetween is obtained bymeans of the above described COG style which directly mounts driving ICson a panel.

Although the first to third embodiments of the present inventionillustrate manufacturing methods of TFT array panels havingsemiconductor patterns made of amorphous silicon, the present inventionmay be applied to a manufacturing method of a TFT array panel having thesemiconductor pattern made of polysilicon.

In this way, under the condition that a wire is covered with aprotective layer, the surface of an organic insulating layer is treatedby the plasma process and then the protective layer is patterned to forma contact exposing the wire. Therefore, it prevents the gases for theplasma process or organic materials from being remained at the contact.Accordingly, the present invention ensures the adhesiveness between theorganic insulating layer and the pixel electrode and minimizes thecontact resistance at a contact.

1. A method of manufacturing a thin film transistor array panel for aliquid crystal display, the method comprising: forming a gate wireincluding a gate line and a gate electrode connected to the gate line;depositing a gate insulating layer; forming a semiconductor layer;forming a data wire including a data line intersecting the gate lines todefine a pixel area, a source electrode connected to the data line andplaced close to the gate electrode, and a drain electrode placedopposite the source electrode with respect to the gate electrodes;depositing a protective layer covering the gate wire or the data wire;forming an organic insulating layer by spin-coating an organicinsulating material on the protective layer; patterning the organicinsulating layer to form a first contact hole exposing the protectivelayer opposite the drain electrode; surface-treating the organicinsulating layer by a plasma process using inactive gas; patterning theprotective layer to form a second contact hole exposing the drainelectrode and located inside the first contact hole; and, forming apixel electrode electrically connected to the drain electrode throughthe first and the second contact holes.
 2. The method of claim 1,wherein the pixel electrode comprises a transparent conductive electrodeor a reflective conductive film.
 3. The method of claim 2, wherein asurface of the organic insulating layer has an unevenness pattern whenthe pixel electrode has the reflective film.
 4. The method of claim 2,wherein the reflective film has an aperture in the pixel area when thepixel electrode comprises both the transparent electrode and thereflective film.
 5. The method of claim 1, wherein the semiconductorlayer comprises amorphous silicon or polysilicon.
 6. The method of claim1, wherein the gate wire further includes a gate pad connected to oneend of the gate line, the data wire further includes a data padconnected to one end of the data line, and the protective layer or thegate insulating layer has a third contact hole exposing the gate pad orthe data pad, and wherein the thin film transistor array panel furthercomprises a subsidiary pad electrically connected to the gate pad or thedata pad through the third contact hole and including substantially thesame layer as the pixel electrode.
 7. The method of claim 1, whereinboth the data wire and the semiconductor layer are formed by a photoetch step using a photoresist pattern with position-dependent thickness.